December 10, 2007
Knowlent Announces Free Download of Powerful Post Processing Environment including Waveform Viewer
Knowlent Corporation, the leading supplier of analog/mixed-signal test bench development technology announced today the availability of a free version of Viper, it's powerful post processing analysis language including waveform viewer. Viper and the waveform viewer are available without support as a free download by registering with Knowlent on their website at www.knowlent.com. Read more »

July 23, 2007
Knowlent brings Advanced Analog/Mixed-Signal Verification Environment to users of Synopsys Discovery™ AMS solutions
Industry’s first test bench development environment aids analysis and verification of complex analog/mixed-signal designs
Knowlent Corporation today announced the release of the Opal TBE™ test bench development and simulation control environment that supports all circuit simulation technologies from Synopsys, Inc. Read more »

June 19, 2006
Knowlent Ensures Analog Sign-off with Latest Opal Verification Platform
New 4.0 Release Offers Testbench for Up-coming PCI Express Gen 2 Standard
Knowlent Corporation, today announced the release of the Opal testbench platform version 4.0 for the validation of high-speed interfaces used in SOC designs implemented in the latest nanometer silicon technologies. Read more »

May 8, 2006
Knowlent Corporation closes second round of financing, names new board members
Knowlent Corporation, an analog testbench software and intellectual property (IP) company, recently closed its second round of funding, bringing total capital raised to $3.6 million. Incubic Venture Fund (Mountain View, Calif.) led the round, with existing investor AsiaTech Ventures (Santa Clara, Calif.) participating. Read more »

September 20, 2005
Knowlent Joins VSIA to improve Analog IP Verification
Knowlent Corp. announced today that it has joined the VSI Alliance (VSIA), the electronic industry's leading IP and SoC standards body. As part of the organization, Knowlent is participating in VSIA's IP Quality group to help improve and standardize the verification of analog IP. Read more »

August 1, 2005
Knowlent Joins ARM Connected Community, High speed interface verification with Electrical Verification IP speed up design of ARM Powered® products.
Knowlent Corporation announced today that it has joined the ARM® Connected Community. As a result, Knowlent gains access to a range of resources to help it market analog verification IP that expedites ARM Powered® products to market. Read more »

June 8, 2005
Knowlent Alleviates XAUI Interface Analog Verification Bottleneck with New OPAL XAUI EVP.
Knowlent Corporation announced today that it has added  XAUI interface analog verification support to its Opal Analog Verification Platforms (EVPs), and is introducing the Opal XAUI EVP. Opal also supports Serial ATA and PCI Express PHY (physical) layer interface verification. Read more »

May 27, 2005
Knowlent Moves to Larger Headquarters in Silicon Valley
Knowlent Corporation announced today that it has moved to larger facilities to accomodate its growing staff and larger customer support facilities for its innovative Opal Analog Verification Platforms (EVPs) that speed up the verification of high-speed electronic design interfaces. The new headquarters are located at 2255 Martin Avenue, Suite H, Santa Clara, CA 95050. Read more »

May 23, 2005
Sandipan Bhanot, CEO of Knowlent Corporation, to speak at Semico's Semiconductor Intellectual Property Conference on the Topic of Analog IP Portability
Sandipan Bhanot, CEO of Knowlent Corporation, a supplier of Analog Verification Platforms(EVPs) and IP that automatically verify the PHY (physical) layer of standard serial and parallel interfaces for electronic designs, will speak on the topic of analog IP portability at Semico's Semiconductor Intellectual Property Conference. Read more »

March 14, 2005
Knowlent Announces Opal Analog Verification Platform and Support for PCI Express, Serial ATA
The rapid adoption of high-speed interface technology has led to a significant change in interface verification requirements. Designers now have to thoroughly verify the electrical layer of the interface because this layer is most vulnerable to failures at higher speeds. Until now... Read more »